The invention herein relates to packet-based network switches; particularly to high-speed multi-port packet-based network switches; and more particularly to memory structures, and associated operational techniques, for high-speed multi-port packet-based network switches.
Present-day throughput demands on packet-based switched networks have created the necessity for switches exhibiting increasingly higher performance. It is most desirable to achieve the transmission speed of the physical transport medium, i.e. to be close to “wire speed.” For high-speed LAN protocols, including those collectively called “Fast Ethernet,” switches typically associated with operations incorporating OSI Reference Model Layer 2 (Data Link Layer) and Layer 1 (Physical Layer) are employed to meet the performance requirements reliably and economically. As the complexity of such devices increases, however, significant trade-offs, for example, between performance, scalability, and affordability may arise.